The present invention pertains to a drive circuit that controls drive current supplied to a load by using a clamp circuit.
In drive circuits that supply drive current for converting electrical energy into thermal energy, depending on the application, drive current that has an accurate output pulsewidth relative to the pulsewidth of the input control signals is required. For example, a design in which ink that is instantly heated to a high temperature and sprayed by a nozzle is used in a so-called inkjet printer to apply ink to printing paper. As the printed dots become finer, higher precision is required to control the timing for spraying the ink. For this reason, in drive circuits for heating ink, high-precision pulse signals must be output for the input pulse control signals.
For such a drive circuit, in addition to circuits that use existing bipolar transistors, drain output type drive circuits that use a high breakdown voltage NMOS have been proposed.
FIG. 5 is a circuit diagram showing one example of such a drive circuit. This drive circuit is constituted with PMOS transistors QP1 and QP2, NMOS transistors QN1, QN2 and QN3, and inverter INV1, as shown.
Transistor QN3 is a high-breakdown voltage NMOS transistor. The resistive element R1 connected to the drain of transistor QN3 is a load resistor. During operation, heat is generated by drive current IL that is output from the drain of transistor QN3 flowing through load resistor R1. This heat is used to heat the ink, for example.
As shown in FIG. 5, in PMOS transistors QP1 and QP2, the sources are connected to source voltage VCC1 and the gates are connected to the drains of each other""s transistors. The drains of NMOS transistors QN1 and QN2 are connected to the drains of transistors QP1 and QP2, respectively, and their sources are grounded. Input signal Sin is applied to the gate of transistor QN1 and the inverted logic signal of input signal Sin is applied to the gate of transistor QN2.
Load resistor R1 is connected between source voltage VCC2 and the drain of NMOS transistor QN3. The gate of transistor QN3 is connected to the drain of transistor QN2 and its source is grounded.
Source voltage VCC1 is 15 V, for example, and source voltage VCC2 is 20-30 V, for example. For the logic level of input signal Sin, for example, the high level is 5 V and the low level is 0 V.
Input signal Sin, is a pulse signal, and transistor QN3 supplies a pulsed current signal to load resistor R1 corresponding to this pulse signal. The operation of this drive circuit is explained below with reference to FIG. 5.
When input signal Sin is low, transistor QN1 is cut off and transistor QN2 is conducting. At this time, the drain of transistor QN2 is held approximately at ground potential, so that transistor QP1 conducts and transistor QP2 cuts off. At this time, node ND1 is held approximately at ground potential GND.
The voltage V01 of node ND1 is applied to the gate of transistor QN3, so that transistor QN3 cuts off and no current flows to load resistor R1.
Next, when input signal Sin goes from low to high, transistor QN1 conducts and transistor QN2 cuts off. Accordingly, transistor QP2 conducts, so that transistor QP1 cuts off and node ND1 is held approximately at source voltage VCC1. At this time, transistor QN3 conducts and drive current IL flows to load resistor R1. The drive current produces heat in load resistor R1.
As stated above, when input signal Sin is low, transistor QN3 cuts off and no drive current is supplied to load resistor R1. On the other hand, when input signal Sin is high, transistor QN3 conducts and drive current IL is supplied to load resistor R1. That is, the timing at which drive current is supplied to load resistor R1 is controlled according to input signal Sin.
In this connection, there is a large punch-through current that accompanies the switching of input signal Sin in the conventional drive circuit, and the amount of power consumed by the circuit will be high. In order to balance the output, that is, to equalize the rise time tr and fall time tf and the rise delay time tPLH and fall delay time tPHL of drive current IL supplied to the load resistor, the size of output transistors QP2 and QN2 and the magnitude of source voltage VCC1 must be adjusted. In addition, they must be readjusted according to load conditions, such as the magnitude of source voltage VCC2, the resistance of load resistor R1, etc. Even if they are adjusted, production variations must be taken into account.
The drive circuit shown in FIGS. 6 and 7 has been proposed to improve this situation.
As shown in FIG. 6, in this drive circuit, constant current sources IS1 and IS2 are added to the drive circuit shown in FIG. 5. As shown in the figure, the sources of PMOS transistors QP3 and QP4 are connected to each other and to current source IS1. The supply current I0 from current source IS1 is input to the sources of transistor QP3 or QP4.
At the same time, current source IS2 is connected between the source and ground potential GND of transistor QN5. Thus, when transistor QN5 is conducting, its source current is determined by supply current I1 from current source IS2.
The drive circuit shown in FIG. 6 operates in approximately the same way as the drive circuit shown in FIG. 5. That is, when input signal Sin is low, transistor QN6 cuts off and no drive current is supplied to load resistor R2. On the other hand, when input signal Sin is high, transistor QN6 conducts and drive current IL is supplied to load resistor R2. The timing of the drive current supplied to load resistor R2 is controlled according to input signal Sin in this way.
FIG. 7 shows an example of another improvement to a drive circuit. As shown in the figure, transistors QP5 and QP6 constitute a current mirror circuit in this drive circuit. The current mirror circuit functions as a timing load circuit for transistors QN7 and QN8. Resistive element R3 is connected between the drain of transistor QP5 and the drain of QN7, and resistive element R4 is connected between the drain of transistor QP6 and the drain of QN8.
This drive circuit also operates in approximately the same way as the drive circuit shown in FIG. 5. That is, when input signal Sin is low, transistor QN9 cuts off and no drive current is supplied to load resistor R5. On the other hand, when input signal Sin is high, transistor QN9 conducts and drive current IL is supplied to load resistor R5. The timing of the drive current supplied to load resistor R5 is controlled according to input signal Sin in this way.
In the drive circuit shown in FIG. 6, punch-through current during switching is limited by current sources IS1 and IS2. However, with this drive circuit, source voltage VCC1 and output currents I0 and I1 of current sources IS1 and IS2 must be adjusted to balance the output, and they must also be readjusted according to load conditions, for example, the value of source voltage VCC2, the resistance of load resistor R2, etc.
And in the drive circuit shown in FIG. 7, punch-through current during switching is limited by resistive elements R3 and R4 that are connected to the drains of transistor QN7 and QN8. However, like the drive circuits shown in FIGS. 5 and 6, the values for resistive elements R3 and R4 and source voltage VCC1 must be adjusted, and in addition, readjusted, according to load conditions, for example, the value of source voltage VCC2, the resistance of load resistor R5, etc., in order to balance output.
The present invention was devised in consideration of these circumstances. Its purpose is to provide a drive circuit that makes circuit adjustment easy, that can maintain a balanced output drive current, and that can supply high precision drive current to the load circuit.
In order to solve the problems, the drive circuit of the present invention supplies drive current to a load resistor that is connected to a first source voltage supply element. It has a current output MOS transistor that is connected in series with the load resistor, a drive part that is connected to a second source voltage supply terminal and that supplies drive current to the gate terminal of the current output MOS transistor, and a clamp circuit that is connected to the second source voltage supply terminal to hold the drain terminal of the current output MOS transistor at a prescribed voltage.
Also, in the present invention, ideally, the clamp circuit comprises a first MOS transistor that is connected between the gate terminal and the drain terminal of the current output MOS transistor, a second MOS transistor whose gate terminal and drain terminal are connected to each other and in which said gate terminal is connected to the gate terminal of the first MOS transistor, a rectifying element that is connected between the gate terminal of the current output MOS transistor and the first MOS transistor or between the first MOS transistor and the drain terminal of the current output MOS transistor, and a current hold means that is connected to the source terminal of the second MOS transistor and that holds the potential of said source terminal at a prescribed voltage.
Also, in the present invention, ideally, the clamp circuit comprises a first current source that supplies current to the second MOS transistor, and the current output MOS transistor and the first and second MOS transistors are NMOS transistors. The voltage hold means is preferably a plurality of diodes that are connected in series between the source terminal and reference potential of the second NMOS transistor.
In addition, the first current source preferably has a first PMOS transistor that is connected between the second source voltage supply terminal and the drain terminal of the second NMOS transistor, a second PMOS whose gate terminal and drain terminal are connected to each other, in which said gate terminal is connected to the gate terminal of the first PMOS transistor and whose source terminal is connected to the second source voltage supply terminal, and a first resistor connected between the drain terminal and the reference potential of the second PMOS transistor.
Also, in the present invention, ideally, the rectifying element is a diode whose anode is connected to the gate terminal of the current output NMOS transistor and whose cathode is connected to the drain terminal of the first NMOS transistor, or a third NMOS transistor connected between the drain terminal of the current output NMOS transistor and the source terminal of the first NMOS transistor and whose gate terminal is connected to the drain terminal of the first NMOS transistor.
Also, in the present invention, ideally, the drive part has a fourth MOS transistor that is connected to the gate terminal of the current output MOS transistor and that supplies a drive signal to the current supply MOS transistor, and a second current source that supplies current to the fourth MOS transistor.
Also in the present invention, ideally, the drive part has a third current source that is connected between the source terminal and the reference potential of the fourth MOS transistor, which is an NMOS transistor, and a fifth NMOS transistor that is connected between the second current source and the reference potential and that operates complementarily with the fourth NMOS transistor. The second current source is connected between the supply terminal of the second power supply voltage and the fifth NMOS transistor. The current source preferably has a third PMOS transistor whose gate terminal and drain terminal are connected, and a fourth PMOS transistor that is connected between the second source voltage supply terminal and the middle point of the connection between gate terminal of the current output MOS transistor and the fourth NMOS transistor, and whose gate terminal is connected to the gate terminal of the third PMOS transistor.
In addition, the drive part preferably has a second resistive element that is connected between the drain terminal of the third PMOS transistor and the drain terminal of the fifth NMOS transistor, and a third resistive element that is connected between the second source voltage supply terminal and the gate terminal of the third PMOS transistor.